1. Field of the Invention
The present invention relates to a data retiming circuit, to an improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop.
2. Description of the Conventional Art
Generally, a receiving unit of a high speed data transmission circuit which uses a high frequency signal uses a data retiming circuit for improving a noise characteristic.
The data retiming circuit which uses a plurality of channels is configured to be made simpler for a desired integration by using one chip.
FIG. 1 is a circuit diagram illustrating a conventional data retiming circuit.
As shown therein, there are connected a PLL 10, a delay unit 20, and a clock selection unit 30. The clock selection unit 30 includes a data sampling unit 31 and a voting circuit 32 for selecting a clock.
However, the conventional data retiming circuit is complex due to a plurality of digital logic circuits. In particular, if there are provided a plurality of channels, it is difficult to integrate into one chip.
There is a conventional method of "Metastability behavior of CMOS ASIC flip-flops in theory and test" (Jens u., etc.,; JSSC Vol-24 No.-1, 1989, USA) which is directed to using a digital logic circuit in order to implement a data retiming method, for thus forming a clock selection unit, so that the construction of the circuit is made complex.